1. Field
The present disclosure relates generally to memory devices, and more specifically, to methods and systems for providing directed bank refresh for volatile memories.
2. Background
Volatile memory is a storage medium that is generally structured as a number of arrays (or banks). Each bank is further arranged as a matrix of “memory cells” in rows and columns, with each column being further divided by the input/output (I/O) width of the memory. Locations within the memory are uniquely specified by bank, row and column. A memory controller may be used to retrieve data from the memory by indicating the data's bank, row and column location. For example, for a quad-bank 128 Mb memory with a 16-bit external data bus, a possible logical address mapping includes a 9-bit column address, a 2-bit bank address and a 12-bit row address.
Prior to reading or writing a memory location, the corresponding row must first be opened. The process of opening a row requires a minimum number of clock cycles, tRCD, which represents the row-to-column delay. Once a row is open, column addresses within that row can be read or written as desired. For some dynamic random access memories (DRAMs), such as synchronous DRAMs (SDRAMs), only one row per bank can be kept open at any one time; a subsequent memory access to be performed within the same bank but at a different row requires closing the current row and opening the new one.
In the case of dynamic volatile memories, each cell must be refreshed, or re-energized, periodically at an average interval, tREF1, in order to maintain data integrity. The cells have to be refreshed because they are designed around capacitors that store electrical charges, which may discharge over time. Refresh is the process of recharging the cells in memory. Cells are generally refreshed one row at a time. A number of methods currently exist that are designed to refresh volatile memories. Some, if not all, of these methods incur high cost in performance and/or power. For example, there are two common methods or techniques that are generally used to control the refresh of volatile memories in modern digital systems. One method relies on the memory to keep track of the row and bank(s) that need to be refreshed using built-in refresh mechanisms that are available on the memory; the other method relies on the memory controller to keep track of the row and bank that need to be refreshed.
The first commonly used method is utilized by the auto-refresh and self-refresh functions of the volatile memories. These functions use the built-in refresh address of the memory. During active use of the memory, when a refresh cycle is required, the memory controller precharges all the banks, and then uses the auto-refresh command to tell the memory to issue an internal refresh cycle. Upon receiving the auto-refresh command, the memory increments the internal refresh address counter and executes the internal refresh cycle. In auto-refresh mode, the memory uses the refresh address in its internal refresh address counter to determine which rows/banks to perform the refresh cycle and cycle through the relevant rows. In one implementation, the internal refresh address counter includes a row address register and a bank address register. The bank address register is incremented to cycle through each of the memory banks with the carry-out of the bank address register causing the row address register to increment. Other implementations do not have a bank address register as all banks are simultaneously refreshed.
A disadvantage of present non-simultaneous bank auto-refresh implementations is that because the memory controller does not know which internal bank will be refreshed, the memory controller is required to close all open rows in each bank prior to issuing an auto-refresh command. As a result, the memory data bus availability during an auto-refresh sequence is zero. At best, this sequence requires tRP+tRFC+tRCD cycles, where tRFC represents a row-precharge delay, tRFC represents the refresh cycle time and tRCD represents the row-to-column delay. For a 133 MHz memory, this could be 16 clock cycles (120 ns). These cycles are sometimes referred to as dead cycles since the memory data bus is not available during this period.
During periods of non-use, the memory controller may place the memory in the self-refresh mode. In the self-refresh mode, the memory uses its own internal clock and refresh address counter to generate refreshes to refresh the row(s) of the memory. This method is good for saving power during idle states since the self-refresh mode can be used. The self-refresh state uses a small amount of power and maintains the contents of the memory by refreshing the memory. Due to the small amount of power needed, this method is typically used for low power applications.
A second method is sometimes used to avoid the dead cycles on the memory data bus mentioned above. According to this second method, control of the refresh is effected via the memory controller. This method does not use any of the built-in refresh mechanisms that are available on the memory. Under this method, at regularly given intervals (tREF1), the memory controller explicitly generates refreshes by opening and closing rows in a sequential manner using bank/row address combinations. The refresh clock, which determines the refresh rate, and the bank/row address combinations are internal to the memory controller. This method is best for high speed/high performance applications. This method allows the memory controller to refresh a particular memory bank while permitting other memory banks to remain open for access, resulting in higher performance; reads and writes to other banks can generally continue in parallel and uninterrupted. The downside to this method is that during system power down or long idle states, when the memory controller is not refreshing the memory, the memory cannot be kept in a self-refresh state. As mentioned above, the self-refresh state is a built-in function of most volatile memories. Since the self-refresh function of the memory increments a refresh address (i.e., the row/bank address) stored in a refresh address counter in the memory, independent of the memory controller, the refresh address maintained by the memory is not consistent or synchronized with the memory controller.
Refresh operations can reduce performance of memory because each refresh cycle forces the memory into an idle state, during which data access is not available. For example, if a refresh cycle is required for a particular memory bank while such bank is in an active state, the bank has to be shut down to allow the refresh operation to take place. Shutting down the bank means that whatever data operations that were to be performed have to be delayed, hence, affecting system performance.
Some existing schemes are available to reduce the performance impact of refresh operations. Such schemes typically involve using a higher than required refresh rate, so that more memory banks can be refreshed within a predetermined refresh period. By having more memory banks refreshed, the chances of having to shut down an active memory bank for refresh are reduced. Using a higher refresh rate, however, has its drawbacks. For example, an increase in refresh rate means memory becomes unavailable for access more often which, in turn, results in lower performance. Also, merely using a higher refresh rate does not always obviate the need to shut down an active memory bank when refresh is required; in some situations, an active memory bank has to be shut down regardless, thus, negating any benefits from using a higher refresh rate.
Hence, it would be desirable to provide more efficient methods and systems for providing directed bank refresh for volatile memories.